MC32MX64GP.h

This is the standard hardware mapping definitions for the PlugAndProgram MC32MX64GP mainboard.


Include this in your firmware project as MC32MX64GP.h


//MC32MX64GP Hardware definitions
//Version 20110224

// Uncomment the next 3 lines for your own applications
// Leave commented for TCPIP Stack application as causes conflicts

//#include
//#include  /* include I/O facilities */
//#include 

// Configuration Bits.

#if defined(THIS_IS_STACK_APPLICATION)  // Only needed for TCPIP Stack application, uncomment for your own application

 #pragma config FNOSC    = PRIPLL          // External with PLL
 #pragma config FPLLIDIV = DIV_2         // PLL Input Divider
 #pragma config FPLLMUL  = MUL_20        // PLL Multiplier
 #pragma config FPLLODIV = DIV_1         // PLL Output Divider
 #pragma config FPBDIV   = DIV_1         // Peripheral Clock divisor
 #pragma config FWDTEN   = OFF           // Watchdog Timer
 #pragma config WDTPS    = PS1           // Watchdog Timer Postscale
 #pragma config FCKSM    = CSDCMD        // Clock Switching & Fail Safe Clock Monitor
 #pragma config OSCIOFNC = OFF           // CLKO Enable
 #pragma config POSCMOD  = HS            // Primary Oscillator
 #pragma config IESO     = ON           // Internal/External Switch-over
 #pragma config FSOSCEN  = ON            // Secondary Oscillator Enable
 #pragma config CP       = OFF           // Code Protect
 #pragma config BWP      = OFF           // Boot Flash Write Protect
 #pragma config PWP      = OFF           // Program Flash Write Protect
 #pragma config ICESEL   = ICS_PGx2      // ICE/ICD Comm Channel Select
 #pragma config DEBUG    = ON           // Debugger Disabled

#endif    // Only needed for TCPIP Stack application, uncomment for your own application

#define GetSystemClock()        (80000000ul)      // Hz
#define GetInstructionClock()    (GetSystemClock()/1)
#define GetPeripheralClock()    (GetInstructionClock()/1)    // Set your divider according to your Peripheral Bus Frequency configuration fuse setting

// Onboard RD6 Combined Tact & LED
// Remember to set as input prior to reading

#define MBLEDTACT        _RD6
#define MBLEDTACTTRIS    _TRISD6
#define MBLEDTACTLAT    _LATD6

#define MBLEDSET() do{MBLEDTACTLAT = 1;} while(0)
#define MBLEDCLR() do{MBLEDTACTLAT = 0;} while(0)
#define MBLEDTOGGLE() do{MBLEDTACTLAT = !MBLEDTACTLAT;} while(0)
#define MBLEDASOUTPUT() do{MBLEDTACTTRIS = 0;} while(0)
#define MBLEDASINPUT() do{MBLEDTACTTRIS = 1;} while(0)
#define MBLEDREAD() (MBLEDTACT)

//////////////////////////////////////////////////////////////////////////////////////

//IO1 General use

// Single pin operations:
#define IO1_1         _RG6
#define IO1_2         _RG7
#define IO1_3         _RG8
#define IO1_4         _RG9
#define IO1_1LAT     _LATG6
#define IO1_2LAT     _LATG7
#define IO1_3LAT     _LATG8
#define IO1_4LAT     _LATG9
#define IO1_1TRIS    _TRISG6
#define IO1_2TRIS     _TRISG7
#define IO1_3TRIS     _TRISG8
#define IO1_4TRIS     _TRISG9

#define IO1_GET() (IO1_4<<3) | (IO1_3<<2) | (IO1_2<<1) | IO1_1)
#define IO1_GETLAT() (IO1_4LAT<<3) | (IO1_3LAT<<2) | (IO1_2LAT<<1) | IO1_1LAT) #define IO1_PUT(a) do{BYTE vTemp = (a); IO1_4LAT = vTemp>>3; IO1_3LAT = vTemp>>2; IO1_2LAT = vTemp>>1; IO1_1LAT = vTemp} while(0)
#define IO1_TRIS(a) do{BYTE vTemp = (a); IO1_4TRIS = vTemp>>3; IO1_3TRIS = vTemp>>2; IO1_2TRIS = vTemp>>1; IO1_1TRIS = vTemp} while(0)

//IO1 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - Change Notification Interrupt: CN08-CN11
// - Parallel Master Port: PMA2-PMA5

//SPI2
#define IO1_SCK2        IO1_1
#define IO1_SDI2        IO1_2
#define IO1_SDO2        IO1_3
#define IO1_SS2            IO1_4
#define IO1_SCK2LAT        IO1_1LAT
#define IO1_SDI2LAT        IO1_2LAT
#define IO1_SDO2LAT        IO1_3LAT
#define IO1_SS2LAT        IO1_4LAT
#define IO1_SCK2TRIS    IO1_1TRIS
#define IO1_SDI2TRIS    IO1_2TRIS
#define IO1_SDO2TRIS    IO1_3TRIS
#define IO1_SS2TRIS        IO1_4TRIS

#define SCK2        IO1_1
#define SDI2        IO1_2
#define SDO2        IO1_3
#define SS2            IO1_4
#define SCK2LAT        IO1_1LAT
#define SDI2LAT        IO1_2LAT
#define SDO2LAT        IO1_3LAT
#define SS2LAT        IO1_4LAT
#define SCK2TRIS    IO1_1TRIS
#define SDI2TRIS    IO1_2TRIS
#define SDO2TRIS    IO1_3TRIS
#define SS2TRIS        IO1_4TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO2 General use

#define IO2_1         _RB4
#define IO2_2         _RB5
#define IO2_3         _RB6
#define IO2_4         _RB7
#define IO2_1LAT     _LATB4
#define IO2_2LAT     _LATB5
#define IO2_3LAT     _LATB6
#define IO2_4LAT     _LATB7
#define IO2_1TRIS     _TRISB4
#define IO2_2TRIS     _TRISB5
#define IO2_3TRIS     _TRISB6
#define IO2_4TRIS     _TRISB7

#define IO2_GET() (IO2_4<<3) | (IO2_3<<2) | (IO2_2<<1) | IO2_1)
#define IO2_GETLAT() (IO2_4LAT<<3) | (IO2_3LAT<<2) | (IO2_2LAT<<1) | IO2_1LAT) #define IO2_PUT(a) do{BYTE vTemp = (a); IO2_4LAT = vTemp>>3; IO2_3LAT = vTemp>>2; IO2_2LAT = vTemp>>1; IO2_1LAT = vTemp} while(0)
#define IO2_TRIS(a) do{BYTE vTemp = (a); IO2_4TRIS = vTemp>>3; IO2_3TRIS = vTemp>>2; IO2_2TRIS = vTemp>>1; IO2_1TRIS = vTemp} while(0)

//IO2 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - Change Notification: CN06-CN07
// - Analogue Comparator Module: C1In-, C1In+
// - Output Compare Module: OCFA

//IO2_1 = AN4
#define IO2_1SetAsAnalogue() do{IO2_1TRIS = 1; AD1PCFGCLR = 0b10000 } while(0)
#define IO2_1SetAsDigital() do{AD1PCFGSET = 0b10000 } while(0)
#define IO2_1GetAnalogueFromScan() (ADC1BUF4)

//IO2_2 = AN5
#define IO2_2SetAsAnalogue() do{IO2_2TRIS = 1; AD1PCFGCLR = 0b100000 } while(0)
#define IO2_2SetAsDigital() do{AD1PCFGSET = 0b100000 } while(0)
#define IO2_2GetAnalogueFromScan() (ADC1BUF5)

//IO2_3 = AN6
#define IO2_3SetAsAnalogue() do{IO2_3TRIS = 1; AD1PCFGCLR = 0b1000000 } while(0)
#define IO2_3SetAsDigital() do{AD1PCFGSET = 0b1000000 } while(0)
#define IO2_3GetAnalogueFromScan() (ADC1BUF6)

//IO2_4 = AN7
#define IO2_4SetAsAnalogue() do{IO2_4TRIS = 1; AD1PCFGCLR = 0b10000000 } while(0)
#define IO2_4SetAsDigital() do{AD1PCFGSET = 0b10000000 } while(0)
#define IO2_4GetAnalogueFromScan() (ADC1BUF7)

//////////////////////////////////////////////////////////////////////////////////////

//IO3 General use
#define IO3_1         _RB0
#define IO3_2         _RB1
#define IO3_3         _RB2
#define IO3_4         _RB3
#define IO3_1LAT     _LATB0
#define IO3_2LAT     _LATB1
#define IO3_3LAT     _LATB2
#define IO3_4LAT     _LATB3
#define IO3_1TRIS     _TRISB0
#define IO3_2TRIS     _TRISB1
#define IO3_3TRIS     _TRISB2
#define IO3_4TRIS     _TRISB3'

#define IO3_GET() (IO3_4<<3) | (IO3_3<<2) | (IO3_2<<1) | IO3_1)
#define IO3_GETLAT() (IO3_4LAT<<3) | (IO3_3LAT<<2) | (IO3_2LAT<<1) | IO3_1LAT) #define IO3_PUT(a) do{BYTE vTemp = (a); IO3_4LAT = vTemp>>3; IO3_3LAT = vTemp>>2; IO3_2LAT = vTemp>>1; IO3_1LAT = vTemp} while(0)
#define IO3_TRIS(a) do{BYTE vTemp = (a); IO3_4TRIS = vTemp>>3; IO3_3TRIS = vTemp>>2; IO3_2TRIS = vTemp>>1; IO3_1TRIS = vTemp} while(0)

//IO3 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - Change Notification: CN02-CN05
// - ADC: VREF+
// - Analogue Comparator Module: CVREF+, CVREF-, C2In-, C2In+
// - SPI1: SS1
// - Parallel Master Port: PMA6

//IO3_1 = AN0
#define IO3_1SetAsAnalogue() do{IO3_1TRIS = 1; AD1PCFGCLR = 0b1 } while(0)
#define IO3_1SetAsDigital() do{AD1PCFGSET = 0b1 } while(0)
#define IO3_1GetAnalogueFromScan() (ADC1BUF0)

//IO3_2 = AN1
#define IO3_2SetAsAnalogue() do{IO3_2TRIS = 1; AD1PCFGCLR = 0b10 } while(0)
#define IO3_2SetAsDigital() do{AD1PCFGSET = 0b10} while(0)
#define IO3_2GetAnalogueFromScan() (ADC1BUF1)

//IO3_3 = AN2
#define IO3_3SetAsAnalogue() do{IO3_3TRIS = 1; AD1PCFGCLR = 0b100 } while(0)
#define IO3_3SetAsDigital() do{AD1PCFGSET = 0b100} while(0)
#define IO3_3GetAnalogueFromScan() (ADC1BUF2)

//IO3_4 = AN3
#define IO3_4SetAsAnalogue() do{IO3_4TRIS = 1; AD1PCFGCLR = 0b1000 } while(0)
#define IO3_4SetAsDigital() do{AD1PCFGSET = 0b1000} while(0)
#define IO3_4GetAnalogueFromScan() (ADC1BUF3)

//////////////////////////////////////////////////////////////////////////////////////

//IO4 General use
#define IO4_1         _RB10
#define IO4_2         _RB11
#define IO4_3         _RB12
#define IO4_4         _RB13
#define IO4_1LAT     _LATB10
#define IO4_2LAT     _LATB11
#define IO4_3LAT     _LATB12
#define IO4_4LAT     _LATB13
#define IO4_1TRIS     _TRISB10
#define IO4_2TRIS     _TRISB11
#define IO4_3TRIS     _TRISB12
#define IO4_4TRIS     _TRISB13

#define IO4_GET() (IO4_4<<3) | (IO4_3<<2) | (IO4_2<<1) | IO4_1)
#define IO4_GETLAT() (IO4_4LAT<<3) | (IO4_3LAT<<2) | (IO4_2LAT<<1) | IO4_1LAT) #define IO4_PUT(a) do{BYTE vTemp = (a); IO4_4LAT = vTemp>>3; IO4_3LAT = vTemp>>2; IO4_2LAT = vTemp>>1; IO4_1LAT = vTemp} while(0)
#define IO4_TRIS(a) do{BYTE vTemp = (a); IO4_4TRIS = vTemp>>3; IO4_3TRIS = vTemp>>2; IO4_2TRIS = vTemp>>1; IO4_1TRIS = vTemp} while(0)

//IO4 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - JTAG: TMS, TDO, TCK, TDI
// - Parallel Master Port: PMA10-PMA13
// - Comparator Voltage Reference: CVRefOut

//IO4_1 = AN10
#define IO4_1SetAsAnalogue() do{IO4_1TRIS = 1; AD1PCFGCLR = 0b1000000000 } while(0)
#define IO4_1SetAsDigital() do{AD1PCFGSET = 0b1000000000 } while(0)
#define IO4_1GetAnalogueFromScan() (ADC1BUF10)

//IO4_2 = AN11
#define IO4_2SetAsAnalogue() do{IO4_2TRIS = 1; AD1PCFGCLR = 0b10000000000 } while(0)
#define IO4_2SetAsDigital() do{AD1PCFGSET = 0b10000000000 } while(0)
#define IO4_2GetAnalogueFromScan() (ADC1BUF11)

//IO4_3 = AN12
#define IO4_3SetAsAnalogue() do{IO4_3TRIS = 1; AD1PCFGCLR = 0b100000000000 } while(0)
#define IO4_3SetAsDigital() do{AD1PCFGSET = 0b100000000000 } while(0)
#define IO4_3GetAnalogueFromScan() (ADC1BUF12)

//IO4_4 = AN13
#define IO4_4SetAsAnalogue() do{IO4_4TRIS = 1; AD1PCFGCLR = 0b1000000000000 } while(0)
#define IO4_4SetAsDigital() do{AD1PCFGSET = 0b1000000000000 } while(0)
#define IO4_4GetAnalogueFromScan() (ADC1BUF13)

//////////////////////////////////////////////////////////////////////////////////////

//IO5 General use

#define IO5_1         _RB14
#define IO5_2         _RF4
#define IO5_3         _RF5
#define IO5_4         _RB8
#define IO5_1LAT     _LATB14
#define IO5_2LAT     _LATF4
#define IO5_3LAT     _LATF5
#define IO5_4LAT     _LATB8
#define IO5_1TRIS     _TRISB14
#define IO5_2TRIS     _TRISF4
#define IO5_3TRIS     _TRISF5
#define IO5_4TRIS     _TRISB8

#define IO5_GET() (IO5_4<<3) | (IO5_3<<2) | (IO5_2<<1) | IO5_1)
#define IO5_GETLAT() (IO5_4LAT<<3) | (IO5_3LAT<<2) | (IO5_2LAT<<1) | IO5_1LAT) #define IO5_PUT(a) do{BYTE vTemp = (a); IO5_4LAT = vTemp>>3; IO5_3LAT = vTemp>>2; IO5_2LAT = vTemp>>1; IO5_1LAT = vTemp} while(0)
#define IO5_TRIS(a) do{BYTE vTemp = (a); IO5_4TRIS = vTemp>>3; IO5_3TRIS = vTemp>>2; IO5_2TRIS = vTemp>>1; IO5_1TRIS = vTemp} while(0)

//IO5 hardware modules
// // Also on this IO but no defines yet for (add later if needed):
// - Change Notification Interrupt: CN17-CN18
// - ADC: AN08, AN14
// - Analogue Comparator Module: C1Out
// - Parallel Master Port: PMA1, PMA8, PMA9, PMALH

//UART2

#define IO5_U2RTS        IO5_1
#define IO5_U2RX        IO5_2
#define IO5_U2TX        IO5_3
#define IO5_U2CTS        IO5_4
#define IO5_U2RTSLAT    IO5_1LAT
#define IO5_U2RXLAT        IO5_2LAT
#define IO5_U2TXLAT        IO5_3LAT
#define IO5_U2CTSLAT    IO5_4LAT
#define IO5_U2RTSTRIS    IO5_1TRIS
#define IO5_U2RXTRIS    IO5_2TRIS
#define IO5_U2TXTRIS    IO5_3TRIS
#define IO5_U2CTSTRIS    IO5_4TRIS

#define U2RTS        IO5_1
#define U2RX        IO5_2
#define U2TX        IO5_3
#define U2CTS        IO5_4
#define U2RTSLAT    IO5_1LAT
#define U2RXLAT        IO5_2LAT
#define U2TXLAT        IO5_3LAT
#define U2CTSLAT    IO5_4LAT
#define U2RTSTRIS    IO5_1TRIS
#define U2RXTRIS    IO5_2TRIS
#define U2TXTRIS    IO5_3TRIS
#define U2CTSTRIS    IO5_4TRIS

//I2C2

#define IO5_SDA2        IO5_2
#define IO5_SCL2        IO5_3
#define IO5_SDA2LAT        IO5_2LAT
#define IO5_SCL2LAT        IO5_3LAT
#define IO5_SDA2TRIS    IO5_2TRIS
#define IO5_SCL2TRIS    IO5_3TRIS

#define SDA2        IO5_2
#define SCL2        IO5_3
#define SDA2LAT        IO5_2LAT
#define SCL2LAT        IO5_3LAT
#define SDA2TRIS    IO5_2TRIS
#define SCL2TRIS    IO5_3TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO6 General use

#define IO6_1         _RF6
#define IO6_2         _RF2
#define IO6_3         _RF3
#define IO6_4         _RD9
#define IO6_1LAT     _LATF6
#define IO6_2LAT     _LATF2
#define IO6_3LAT     _LATF3
#define IO6_4LAT     _LATD9
#define IO6_1TRIS     _TRISF6
#define IO6_2TRIS     _TRISF2
#define IO6_3TRIS     _TRISF3
#define IO6_4TRIS     _TRISD9

#define IO6_GET() (IO6_4<<3) | (IO6_3<<2) | (IO6_2<<1) | IO6_1)
#define IO6_GETLAT() (IO6_4LAT<<3) | (IO6_3LAT<<2) | (IO6_2LAT<<1) | IO6_1LAT) #define IO6_PUT(a) do{BYTE vTemp = (a); IO6_4LAT = vTemp>>3; IO6_3LAT = vTemp>>2; IO6_2LAT = vTemp>>1; IO6_1LAT = vTemp} while(0)
#define IO6_TRIS(a) do{BYTE vTemp = (a); IO6_4TRIS = vTemp>>3; IO6_3TRIS = vTemp>>2; IO6_2TRIS = vTemp>>1; IO6_1TRIS = vTemp} while(0)

//IO6 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// Interrupts: INT2
// Input capture: IC2

//UART1

#define IO6_U1RTS        IO6_1
#define IO6_U1RX        IO6_2
#define IO6_U1TX        IO6_3
#define IO6_U1CTS        IO6_4
#define IO6_U1RTSLAT    IO6_1LAT
#define IO6_U1RXLAT        IO6_2LAT
#define IO6_U1TXLAT        IO6_3LAT
#define IO6_U1CTSLAT    IO6_4LAT
#define IO6_U1RTSTRIS    IO6_1TRIS
#define IO6_U1RXTRIS    IO6_2TRIS
#define IO6_U1TXTRIS    IO6_3TRIS
#define IO6_U1CTSTRIS    IO6_4TRIS

#define U1RTS        IO6_1
#define U1RX        IO6_2
#define U1TX        IO6_3
#define U1CTS        IO6_4
#define U1RTSLAT    IO6_1LAT
#define U1RXLAT        IO6_2LAT
#define U1TXLAT        IO6_3LAT
#define U1CTSLAT    IO6_4LAT
#define U1RTSTRIS    IO6_1TRIS
#define U1RXTRIS    IO6_2TRIS
#define U1TXTRIS    IO6_3TRIS
#define U1CTSTRIS    IO6_4TRIS

// SPI1
// Note:
// - The actual SS1 Interrupt pin is not on this IO.  Therefore this SS1 define can only be used for controlling slave SPI devices,
//   use SPI2 if you need to run the MC32MX64GP as an SPI Slave with hardware SS interrupts

//SPI1

#define IO6_SCK1        IO6_1
#define IO6_SDI1        IO6_2
#define IO6_SDO1        IO6_3
#define IO6_SS1            IO6_4
#define IO6_SCK1LAT        IO6_1LAT
#define IO6_SDI1LAT        IO6_2LAT
#define IO6_SDO1LAT        IO6_3LAT
#define IO6_SS1LAT        IO6_4LAT
#define IO6_SCK1TRIS    IO6_1TRIS
#define IO6_SDI1TRIS    IO6_2TRIS
#define IO6_SDO1TRIS    IO6_3TRIS
#define IO6_SS1TRIS        IO6_4TRIS

#define SCK1        IO6_1
#define SDI1        IO6_2
#define SDO1        IO6_3
#define SS1            IO6_4
#define SCK1LAT        IO6_1LAT
#define SDI1LAT        IO6_2LAT
#define SDO1LAT        IO6_3LAT
#define SS1LAT        IO6_4LAT
#define SCK1TRIS    IO6_1TRIS
#define SDI1TRIS    IO6_2TRIS
#define SDO1TRIS    IO6_3TRIS
#define SS1TRIS        IO6_4TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO7 General use

#define IO7_1         _RF0
#define IO7_2         _RG3
#define IO7_3         _RG2
#define IO7_4         _RF1
#define IO7_1LAT     _LATF0
#define IO7_2LAT     _LATG3
#define IO7_3LAT     _LATG2
#define IO7_4LAT     _LATF1
#define IO7_1TRIS     _TRISF0
#define IO7_2TRIS     _TRISG3
#define IO7_3TRIS     _TRISG2
#define IO7_4TRIS     _TRISF1

#define IO7_GET() (IO7_4<<3) | (IO7_3<<2) | (IO7_2<<1) | IO7_1)
#define IO7_GETLAT() (IO7_4LAT<<3) | (IO7_3LAT<<2) | (IO7_2LAT<<1) | IO7_1LAT) #define IO7_PUT(a) do{BYTE vTemp = (a); IO7_4LAT = vTemp>>3; IO7_3LAT = vTemp>>2; IO7_2LAT = vTemp>>1; IO7_1LAT = vTemp} while(0)
#define IO7_TRIS(a) do{BYTE vTemp = (a); IO7_4TRIS = vTemp>>3; IO7_3TRIS = vTemp>>2; IO7_2TRIS = vTemp>>2; IO7_1TRIS = vTemp} while(0)

//IO7 hardware modules

// I2C1

#define IO7_SDA1        IO7_2
#define IO7_SCL1        IO7_3
#define IO7_SDA1LAT        IO7_2LAT
#define IO7_SCL1LAT        IO7_3LAT
#define IO7_SDA1TRIS    IO7_2TRIS
#define IO7_SCL1TRIS    IO7_3TRIS

#define SDA1        IO7_2
#define SCL1        IO7_3
#define SDA1LAT        IO7_2LAT
#define SCL1LAT        IO7_3LAT
#define SDA1TRIS    IO7_2TRIS
#define SCL1TRIS    IO7_3TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO8 General use

#define IO8_1         _RB9
#define IO8_2         _RD7
#define IO8_3         _RD8
#define IO8_4         _RD10
#define IO8_1LAT     _LATB9
#define IO8_2LAT     _LATD7
#define IO8_3LAT     _LATD8
#define IO8_4LAT     _LATD10
#define IO8_1TRIS     _TRISB9
#define IO8_2TRIS     _TRISD7
#define IO8_3TRIS     _TRISD8
#define IO8_4TRIS     _TRISD10

#define IO8_GET() (IO8_4<<3) | (IO8_3<<2) | (IO8_2<<1) | IO8_1)
#define IO8_GETLAT() (IO8_4LAT<<3) | (IO8_3LAT<<2) | (IO8_2LAT<<1) | IO8_1LAT) #define IO8_PUT(a) do{BYTE vTemp = (a); IO8_4LAT = vTemp>>3; IO8_3LAT = vTemp>>2; IO8_2LAT = vTemp>>1; IO8_1LAT = vTemp} while(0)
#define IO8_TRIS(a) do{BYTE vTemp = (a); IO8_4TRIS = vTemp>>3; IO8_3TRIS = vTemp>>2; IO8_2TRIS = vTemp>>1; IO8_1TRIS = vTemp} while(0)

//IO8 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - Change Notification Interrupt: CN16
// - Interrupts: INT1, INT3
// - Input Capture Module: IC1, IC3
// - ADC: AN09
// - Analogue Comparator: C2Out
// - Parallel Master Port: PMA7, PMA15, PMCS2

//Nothing defined here..

//////////////////////////////////////////////////////////////////////////////////////

//IO9 General use

#define IO9_1         _RD0
#define IO9_2         _RD1
#define IO9_3         _RD2
#define IO9_4         _RD3
#define IO9_1LAT     _LATD0
#define IO9_2LAT     _LATD1
#define IO9_3LAT     _LATD2
#define IO9_4LAT     _LATD3
#define IO9_1TRIS     _TRISD0
#define IO9_2TRIS     _TRISD1
#define IO9_3TRIS     _TRISD2
#define IO9_4TRIS     _TRISD3

#define IO9_GET() (IO9_4<<3) | (IO9_3<<2) | (IO9_2<<1) | IO9_1)
#define IO9_GETLAT() (IO9_4LAT<<3) | (IO9_3LAT<<2) | (IO9_2LAT<<1) | IO9_1LAT) #define IO9_PUT(a) do{BYTE vTemp = (a); IO9_4LAT = vTemp>>3; IO9_3LAT = vTemp>>2; IO9_2LAT = vTemp>>1; IO9_1LAT = vTemp} while(0)
#define IO9_TRIS(a) do{BYTE vTemp = (a); IO9_4TRIS = vTemp>>3; IO9_3TRIS = vTemp>>2; IO9_2TRIS = vTemp>>1; IO9_1TRIS = vTemp} while(0)

//IO8 hardware modules

// Output Compare Module

#define IO9_OC1            IO9_1
#define IO9_OC2            IO9_2
#define IO9_OC3            IO9_3
#define IO9_OC4            IO9_4
#define IO9_OC1LAT        IO9_1LAT
#define IO9_OC2LAT        IO9_2LAT
#define IO9_OC3LAT        IO9_3LAT
#define IO9_OC4LAT        IO9_4LAT
#define IO9_OC1TRIS        IO9_1TRIS
#define IO9_OC2TRIS        IO9_2TRIS
#define IO9_OC3TRIS        IO9_3TRIS
#define IO9_OC4TRIS        IO9_4TRIS

#define OC1            IO9_1
#define OC2            IO9_2
#define OC3            IO9_3
#define OC4            IO9_4
#define OC1LAT        IO9_1LAT
#define OC2LAT        IO9_2LAT
#define OC3LAT        IO9_3LAT
#define OC4LAT        IO9_4LAT
#define OC1TRIS        IO9_1TRIS
#define OC2TRIS        IO9_2TRIS
#define OC3TRIS        IO9_3TRIS
#define OC4TRIS        IO9_4TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO10 General use

#define IO10_1         _RD4
#define IO10_2         _RD5
#define IO10_3         _RB15
#define IO10_4         _RD11
#define IO10_1LAT     _LATD4
#define IO10_2LAT     _LATD5
#define IO10_3LAT     _LATB15
#define IO10_4LAT     _LATD11
#define IO10_1TRIS     _TRISD4
#define IO10_2TRIS     _TRISD5
#define IO10_3TRIS     _TRISB15
#define IO10_4TRIS     _TRISD11

#define IO10_GET() (IO10_4<<3) | (IO10_3<<2) | (IO10_2<<1) | IO10_1)
#define IO10_GETLAT() (IO10_4LAT<<3) | (IO10_3LAT<<2) | (IO10_2LAT<<1) | IO10_1LAT) #define IO10_PUT(a) do{BYTE vTemp = (a); IO10_4LAT = vTemp>>3; IO10_3LAT = vTemp>>2; IO10_2LAT = vTemp>>1; IO10_1LAT = vTemp} while(0)
#define IO10_TRIS(a) do{BYTE vTemp = (a); IO10_4TRIS = vTemp>>3; IO10_3TRIS = vTemp>>2; IO10_2TRIS = vTemp>>1; IO10_1TRIS = vTemp} while(0)

//IO10 hardware modules
// Also on this IO but no defines yet for (add later if needed):
// - Change Notification Interrupt: CNCN12-CN14
// - Interrupts: INT4
// - Input Capture Module: IC4, IC5
// - Output Compare Module: OC5, OCFB
// - ADC: AN09
// - Analogue Comparator: C2Out

// Parallel Master port
#define IO10_PMWR        IO10_1
#define IO10_PMRD        IO10_2
#define IO10_PMA0        IO10_3
#define IO10_PMALL        IO10_3
#define IO10_PMA14        IO10_4
#define IO10_PMCS1        IO10_4
#define IO10_PMWRLAT    IO10_1LAT
#define IO10_PMRDLAT    IO10_2LAT
#define IO10_PMA0LAT    IO10_3LAT
#define IO10_PMALLLAT    IO10_3LAT
#define IO10_PMA14LAT    IO10_4LAT
#define IO10_PMCS1LAT    IO10_4LAT
#define IO10_PMWRTRIS    IO10_1TRIS
#define IO10_PMRDTRIS    IO10_2TRIS
#define IO10_PMA0TRIS    IO10_3TRIS
#define IO10_PMALLTRIS    IO10_3TRIS
#define IO10_PMA14TRIS    IO10_4TRIS
#define IO10_PMCS1TRIS    IO10_4TRIS

#define PMWR        IO10_1
#define PMRD        IO10_2
#define PMA0        IO10_3
#define PMALL        IO10_3
#define PMA14        IO10_4
#define PMCS1        IO10_4
#define PMWRLAT        IO10_1LAT
#define PMRDLAT        IO10_2LAT
#define PMA0LAT        IO10_3LAT
#define PMALLLAT    IO10_3LAT
#define PMA14LAT    IO10_4LAT
#define PMCS1LAT    IO10_4LAT
#define PMWRTRIS    IO10_1TRIS
#define PMRDTRIS    IO10_2TRIS
#define PMA0TRIS    IO10_3TRIS
#define PMALLTRIS    IO10_3TRIS
#define PMA14TRIS    IO10_4TRIS
#define PMCS1TRIS    IO10_4TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO11 General use

#define IO11_1         _RE0
#define IO11_2         _RE1
#define IO11_3         _RE2
#define IO11_4         _RE3
#define IO11_1LAT     _LATE0
#define IO11_2LAT     _LATE1
#define IO11_3LAT     _LATE2
#define IO11_4LAT     _LATE3
#define IO11_1TRIS     _TRISE0
#define IO11_2TRIS     _TRISE1
#define IO11_3TRIS     _TRISE2
#define IO11_4TRIS     _TRISE3

#define IO11_GET() (IO11_4<<3) | (IO11_3<<2) | (IO11_2<<1) | IO11_1)
#define IO11_GETLAT() (IO11_4LAT<<3) | (IO11_3LAT<<2) | (IO11_2LAT<<1) | IO11_1LAT) #define IO11_PUT(a) do{BYTE vTemp = (a); IO11_4LAT = vTemp>>3; IO11_3LAT = vTemp>>2; IO11_2LAT = vTemp>>1; IO11_1LAT = vTemp} while(0)
#define IO11_TRIS(a) do{BYTE vTemp = (a); IO11_4TRIS = vTemp>>3; IO11_3TRIS = vTemp>>2; IO11_2TRIS = vTemp>>1; IO11_1TRIS = vTemp} while(0)

//IO11 hardware modules

// Parallel Master port
#define IO11_PMD0        IO11_1
#define IO11_PMD1        IO11_2
#define IO11_PMD2        IO11_3
#define IO11_PMD3        IO11_4
#define IO11_PMD0LAT    IO11_1LAT
#define IO11_PMD1LAT    IO11_2LAT
#define IO11_PMD2LAT    IO11_3LAT
#define IO11_PMD3LAT    IO11_4LAT
#define IO11_PMD0TRIS    IO11_1TRIS
#define IO11_PMD1TRIS    IO11_2TRIS
#define IO11_PMD2TRIS    IO11_3TRIS
#define IO11_PMD3TRIS    IO11_4TRIS

#define PMD0        IO11_1
#define PMD1        IO11_2
#define PMD2        IO11_3
#define PMD3        IO11_4
#define PMD0LAT        IO11_1LAT
#define PMD1LAT        IO11_2LAT
#define PMD2LAT        IO11_3LAT
#define PMD3LAT        IO11_4LAT
#define PMD0TRIS    IO11_1TRIS
#define PMD1TRIS    IO11_2TRIS
#define PMD2TRIS    IO11_3TRIS
#define PMD3TRIS    IO11_4TRIS

//////////////////////////////////////////////////////////////////////////////////////

//IO12 General use

#define IO12_1         _RE4
#define IO12_2         _RE5
#define IO12_3         _RE6
#define IO12_4         _RE7
#define IO12_1LAT     _LATE4
#define IO12_2LAT     _LATE5
#define IO12_3LAT     _LATE6
#define IO12_4LAT     _LATE7
#define IO12_1TRIS     _TRISE4
#define IO12_2TRIS     _TRISE5
#define IO12_3TRIS     _TRISE6
#define IO12_4TRIS     _TRISE7

#define IO12_GET() (IO12_4<<3) | (IO12_3<<2) | (IO12_2<<1) | IO12_1)
#define IO12_GETLAT() (IO12_4LAT<<3) | (IO12_3LAT<<2) | (IO12_2LAT<<1) | IO12_1LAT) #define IO12_PUT(a) do{BYTE vTemp = (a); IO12_4LAT = vTemp>>3; IO12_3LAT = vTemp>>2; IO12_2LAT = vTemp>>1; IO12_1LAT = vTemp} while(0)
#define IO12_TRIS(a) do{BYTE vTemp = (a); IO12_4TRIS = vTemp>>3; IO12_3TRIS = vTemp>>2; IO12_2TRIS = vTemp>>1; IO12_1TRIS = vTemp} while(0)

//IO12 hardware modules

// Parallel Master port
#define IO12_PMD4        IO12_1
#define IO12_PMD5        IO12_2
#define IO12_PMD6        IO12_3
#define IO12_PMD7        IO12_4
#define IO12_PMD4LAT    IO12_1LAT
#define IO12_PMD5LAT    IO12_2LAT
#define IO12_PMD6LAT    IO12_3LAT
#define IO12_PMD7LAT    IO12_4LAT
#define IO12_PMD4TRIS    IO12_1TRIS
#define IO12_PMD5TRIS    IO12_2TRIS
#define IO12_PMD6TRIS    IO12_3TRIS
#define IO12_PMD7TRIS    IO12_4TRIS

#define PMD4        IO12_1
#define PMD5        IO12_2
#define PMD6        IO12_3
#define PMD7        IO12_4
#define PMD4LAT        IO12_1LAT
#define PMD5LAT        IO12_2LAT
#define PMD6LAT        IO12_3LAT
#define PMD7LAT        IO12_4LAT
#define PMD4TRIS    IO12_1TRIS
#define PMD5TRIS    IO12_2TRIS
#define PMD6TRIS    IO12_3TRIS
#define PMD7TRIS    IO12_4TRIS

//////////////////////////////////////////////////////////////////////////////////////